Memory arrays with hierarchical or “segmented” bitline architectures have been developed in recent years in order to increase the integration density of memory chips. This architecture allows for a reduced number of space-consuming sense amplifiers for a given number of memory cells, thus reducing chip size or increasing memory capacity for a given sized chip.
In a hierarchical bitline architecture, each column within a memory cell array includes a number of equal length local bitlines (LBLs), directly connected to the memory cells, and to global bitlines (GBLs), for example, composed of a high conductivity metal disposed at a higher fabrication layer than the local bitlines. By way of example, each local bitline may connect to several hundred memory cells, while each global bitline is connected directly to a sense amplifier and is selectively coupled to a number of local bitlines in a common column by a number of switches. To access (e.g., read) a memory cell connected to a particular local bitline, the switch connecting that local bitline to the global bitline is closed, while the other switches in the column are open.
In order for a hierarchical bitline memory array, such as a static random access memory (SRAM) array, to maintain functionality and high speed performance over a range of power supplies, temperature and process variations, global read control signals that maintain timing relationships (tracking) to local read control signals of the respective memory subarrays are desirable. Prior attempts at synchronization have employed programmable delays based on a grid clock or system clock to generate the global read control signals. With such implementations, however, there is no inherent tracking between the global and local control signals.
Thus, provided herein are novel techniques for synchronizing global and local read control signals for a memory array configured with multiple memory subarrays, such as a hierarchical bitline SRAM architecture.